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?1 CXA1396D e94521a79-ps 8-bit 125 msps flash a/d converter sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. av ee linv dv ee dgnd1 dgnd2 (lsb) d0 d1 d2 d3 d4 d5 d6 (msb) d7 dgnd2 dgnd1 dv ee minv clk clk 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 v rt av ee av ee agnd v in agnd v rm agnd v in agnd av ee av ee v rb (top view) description the CXA1396D are 8-bit ultrahigh-speed flash a/d converter ics capable of digitizing analog signals at the maximum rate of 125 msps. the digital i/o levels of these a/d converters are compatible with the ecl 100k/10kh/10k. the CXA1396D is pin-compatible with the earlier model cx20116. they can replace the earlier models respectively, without any design changes, in most cases. compared with the earlier models, these new models have been greatly improved in performance, by incorporating advanced process, new circuit design and carefully considered layout. features ultrahigh-speed operation with maximum conversion rate of 125 msps (min.) wide analog input bandwidth: 200mhz (min. for full-scale input) low power consumption: 870mw (typ.) single power supply: ?.2v low input capacitance built-in integral linearity compensation circuit low error rate operable at 50% clock duty cycle good temperature charactcristics capable of driving 50 loads structure bipolar silicon monolithic ic applications digital oscilloscopes hdtv (high-definition tvs) other apparatus requiring ultrahigh-speed a/d conversion pin configuration pins without name are nc pins (not connected). 42 pin dip (ceramic)
? 2 CXA1396D absolute maximum ratings (ta = 25 c) supply voltage av ee , dv ee ? to +0.5 v analog input voltage v in ?.7 to +0.5 v reference input voltage v rt , v rb , v rm ?.7 to +0.5 v v rt ?v rb 2.5 v digital input voltage clk, clk, minv, linv ? to +0.5 v clk ?clk 2.7 v v rm pin input curent i vrm ? to +3 ma digital output current id 0 to id 7 ?0 to 0 ma storage temperature tstg ?5 to +150 c recommended operating conditions min. typ. max. unit supply voltage av ee , dv ee ?.5 ?.2 ?.95 v av ee ?dv ee ?.05 0 +0.05 v agnd ?dgnd ?.05 0 +0.05 v reference input voltage v rt ?.1 0 +0.1 v v rb ?.2 ?.0 ?.8 v analog input voltage v in v rb v rt pulse width of clock t pw1 4.0 ns t pw0 4.0 ns operating temperature ta ?0 +75 c
? 3 CXA1396D block diagram 2 5 5 1 2 6 1 2 7 1 2 8 1 2 9 1 9 1 1 9 2 1 9 3 2 5 4 6 3 6 4 6 5 1 2 c l o c k d r i v e r r 3 r 1 r 2 r / 2 r r r r r r r r r r r r r r r / 2 d 7 ( m s b ) d 6 d 4 d 3 d 5 d 2 d 1 d 0 ( l s b ) o u t p u t e n c o d e l o g i c m i n v v r t v i n v r m v i n v r b c l k c l k l i n v c o m p a r a t o r
? 4 CXA1396D pin description and i/o pin equivalent circuit analog gnd. used as gnd for input buffers and latches of comparators. isolated from dgnd1, dgnd2. 29, 31, 33, 35 agnd 0v 1, 25, 26, 38, 39 21 20 5, 16 6, 15 dgnd2 0v 4, 17 dv ee ?.2v dgnd1 0v clk clk i ecl av ee ?.2v analog v ee . ?.2v (typ.). internally connected with dv ee (resistance: 4 to 6 ). a ceramic chip capacitor of at least 0.1 f should be used to connect to agnd and be placed near the pins. clk input complementary input to clk. with open connection, kept at threshold voltage (?.3v). device is operable without clk input, but use of omplementary inputs of clk and clk is recommended to obtain the stable high-speed operation. digital gnd for internal circuits. digital gnd for output transistors. digital v ee . internally connected with av ee (resistance: 4 to 6 ). a ceramic chip capacitor of at least 0.1 f should be used to connect to dgnd near the pins. pin no. symbol i/o standard voltage level equivalent circuit description r r r r r r d g n d 1 c l k c l k d v e e
? 5 CXA1396D lsb of data outputs. external pull-down resistor is required. data outputs. external pull-down resistors are required. msb of data outputs. external pull-down resistor is required. input pin for d0 (lsb) to d6 output polarity inversion (see output code table). with open connection, kept at "l" level. input pin for d7(msb) output polarity inversion (see output code table). with open connection, kept at "l" level. analog input pins. these two pins must be connected externally, since they are not internally connected. see application note for precautions. 7 14 3 18 30, 34 v in i v rt to v rb minv i ecl linv i ecl d7 8 9 10 11 12 13 d1 d2 d3 d4 d5 d6 d0 o ecl pin no. symbol i/o standard voltage level equivalent circuit description d g n d 2 d v e e d i r r r r l i n v o r m i n v d g n d 1 d v e e 1 . 3 v a g n d a v e e v i n v i n
? 6 CXA1396D reference voltage (bottom). typically ?v. a ceramic capacitor of at least 0.1 f and a tantalum capacitor of at least 10 f should be used to connect to agnd near the pins. reference voltage mid point. can be used as a pin for integral linearity compensation. reference voltage (top). typically 0v. when a voltage except for agnd is applied to this pin, a ceramic capacitor of at least 0.1 f and a tantalum capacitor of at least 10 f should be used to connect to agnd near the pins. unused pins. no internal connections have been made to these pins. connecting them to agnd or dgnd on pc board is recommended. 23 32 41 2, 19, 22, 24, 27, 28, 36, 37, 40, 42 nc v rt i 0v v rm i v rb /2 v rb i ?v pin no. symbol i/o standard voltage level equivalent circuit description . . . c o m p a r a t o r 1 c o m p a r a t o r 2 c o m p a r a t o r 1 2 7 c o m p a r a t o r 1 2 8 c o m p a r a t o r 1 2 9 c o m p a r a t o r 1 3 0 c o m p a r a t o r 2 5 5 . . . . . . . r / 2 r r r r r r r r / 2 r 3 r 2 r 1 v r t v r m v r b
? 7 CXA1396D electrical characteristics (ta = 25 c, av ee = dv ee = ?.2v, v rt = 0v, v rb = ?v) item resolution dc characteristics integral linearity error differential linearity error analog input analog input capacitance analog input resistance input bias current reference inputs reference resistance offset voltage v rt v rb digital inputs logic h level logic l level logic h current logic l current input capacitance switching characteristics maximum conversion rate aperture jitter sampling delay output delay h pulse width of clock l pulse width of clock digital outputs logic h level logic l level output rising time output falling time dynamic characteristics input bandwidth s/n ratio error rate differential gain error differential phase error power supply supply current power consumption * 2 n e il e dl c in r in i in r ref e ot e ob v ih v il i ih i il fc taj tds tdo t pw1 t pw0 v oh v ol tr tf dg dp i ee pd fc = 125msps fc = 125msps v in = ?v + 0.07vrms v in = ?v input connected to ?.8v input connected to ?.6v error rate 10 ? tps * 1 r l = 50 to ?v r l = 50 to ?v r l = 50 to ?v, 20% to 80% r l = 50 to ?v, 80% to 20% v in = 2vp-p, 3db down input = 1mhz, fs clock = 125mhz input = 31.5mhz, fs clock = 125mhz input = 31.249mhz, fs error > 16lsb clock = 125mhz ntsc 40ire mod.ramp, fc = 125msps 75 8 0 ?.13 0 ?0 125 3.0 4.0 4.0 ?.10 200 ?30 8 0.3 0.3 17 190 130 110 19 15 7 10 1.5 3.6 0.8 1.0 46 40 1.0 0.5 ?60 870 0.5 0.5 320 155 32 24 ?.50 50 50 4.2 ?.62 10 ? bits lsb lsb pf k a mv mv v v a a pf msps ps ns ns ns ns v v ns ns mhz db db tps * 1 % deg ma mw symbol condition min. typ. max. unit { { } { * 1 tps: times per sample * 2 pd = i ee v ee + r ref (v rt ?v rb ) 2
? 8 CXA1396D output code table v in * 0v ?v ?v 0 1 127 128 254 255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 : : 0 1 1 1 1 1 0 0 0 0 : : 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 : : 1 1 1 1 1 0 0 0 0 0 : : 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0 : : 0 0 0 0 0 1 1 1 1 1 : : 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 : : 1 0 0 0 0 0 1 1 1 1 : : 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 step minv 1 linv 1 d7 d0 d7 d0 d7 d0 d7 d0 0 1 1 0 0 0 * v rt = 0v, v rb = ?v timing diagram t d s t r t f 8 0 % 2 0 % 8 0 % n + 1 2 0 % n n 1 t d o t p w 0 t p w 1 n + 1 n + 2 n a n a l o g i n c l k c l k d i g i t a l o u t
? 9 CXA1396D electrical characteristics test circuit maximum conversion rate test circuit c o m p a r a t o r a > b p u l s e c o u n t e r c x a 1 3 9 6 d s i g n a l s o u r c e e c l l a t c h e c l l a t c h 1 / 4 + s i g n a l s o u r c e f c l k 4 1 k h z 2 v p - p s i n e w a v e f c l k v i n c l k c l k 8 d a t a 1 6 a b differential gain error test circuit differential phase error test circuit d u t c x a 1 3 9 6 d e c l l a t c h 1 0 b i t d / a v e c t o r s c o p e d e l a y a m p n t s c s i g n a l s o u r c e s g ( c w ) 5 0 c l k c l k 1 0 w v i n 8 8 v b b d g . d p ( c x 2 0 2 0 2 a - 1 ) d u t c x a 1 3 9 6 d a < b a > b c o m p a r a t o r a 8 a 1 a 0 b 8 b 1 b 0 t o t o b u f f e r c o n t r o l l e r d v m 8 8 8 " 1 " " 0 " 0 0 0 0 0 0 0 0 t o 1 1 1 1 1 1 1 0 c l k ( 1 2 5 m h z ) v i n + v v s 2 s 1 s 1 : a < b : o n s 2 : a > b : o n integral linearity error test circuit differential linearity error test circuit
? 10 CXA1396D power supply current test circuit analog input bias current test circuit 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 1 c x a 1 3 9 6 d a a 1 v i i n 2 v i e e 5 . 2 v 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 sampling delay test circuit aperture jitter test circuit aperture jitter test method c x a 1 3 9 6 d o s c 1 f : v a r i a b l e o s c 2 l o g i c a n a l i z e r 6 7 . 5 m h z 6 7 . 5 m h z a m p e c l b u f f e r c l k v i n 8 f r 1 0 2 4 s a m p l e s v i n s ( l s b ) c l k v i n c l k t d v d t 0 v 1 v 2 v 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 a p e r t u r e j i t t e r apeature jitter is defined as follows: taj = s / = s /( ), where s (unit : lsb) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. ? t ? v 2 256 2 f
? 11 CXA1396D 8-bit, 125msps adc evaluation board description the CXA1396D evaluation board with dac is a tool for customers to evaluate the performance of the CXA1396D (8-bit, 125msps, high-speed a/d converter). in addition to indispensable features such as the reference voltage generator, this tool equips two sets of analog inputs (the direct input and the buffer amplifier input), the input voltage offset generator, the clock decimator, the output data latches, the 10-bit high-speed dac, and the 20-pin cable connector for digital outputs. this evaluation board provides full performance of the CXA1396D and it is designed to facilitate evaluation. features resolution: 8bits maximum conversion rate: 125msps supply voltage: +5.0v, ?.2v, ?.0v two analog inputs (direct input, buffer amplifier input) clock level converter: sine wave to ecl level signal reference voltage adjustment circuit for the a/d converter built-in clock frequency decimation circuit: (1/1 to 1/16) fig. 1. block diagram b u f f e r d a t a l a t c h l i n v m i n v v r b v r m v i n c l k c x a 1 3 9 6 d v i n o f f s e t d e c i m a t o r d / a c o n v e r t e r v r b 2 v s w 3 c l k s w 1 s w 2 l h 5 . 2 v ( a ) 5 . 2 v ( a ) v r 2 ( 2 k ) v r 1 ( 2 k ) a m p . i n d i r . i n c l k 2 4 0 5 1 5 1 0 . 1 j 1 a b c d v r 3 ( 1 k ) 1 k 8 8 8 ( d 7 t o d 0 ) d i g i t a l o u t ( c o n n e c t o r ) 8 ( d 7 t o d 0 ) 2 ( c l k . c l k ) c l k d / a o u t 1 / 1 t o 1 / 1 6 x ( 2 ) 5 . 2 v ( d ) d g n d 2 v ( d ) 5 . 2 v ( a ) a g n d + 5 v
? 12 CXA1396D supply current item min. typ. max. unit ?.2v +5.0v ?.0v 0.85 15 0.45 1.0 30 0.6 a ma a ( note: supply current ?.0v is the value when rn10, rn11 and rn12 are not mounted.) analog input (dir. in, amp. in) item min. typ. max. unit input voltage (dir. in) (amp. in) * 1 input impedance ?.0 ?.5 50 0 +0.5 v v ( * 1 : adjustable by vr1) clock input (clk) item min. typ. max. unit input voltage (peak to peak) input impedance 1.0 50 vp-p digital output (d0 to d7) ecl 10kh level clock output ecl 10kh level, complementary output output code table v in 1 1 1 1 1 1 1 1 1 0 : : 1 0 0 0 0 0 1 1 1 1 : : 0 0 0 0 1 0 0 0 0 0 0v : : : : : : : : ?v 1 0 0 0 0 1 0 0 0 1 : : 1 1 1 1 1 0 0 0 0 0 : : 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0 : : 0 0 0 0 0 1 1 1 1 1 : : 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 : : 0 1 1 1 1 1 0 0 0 0 : : 1 1 1 1 0 1 1 1 1 1 minv linv 0 1 0 0 1 0 1 1
? 13 CXA1396D fig. 2. timing chart n 1 n n 2 n 1 n t d h 1 . 8 n s ( t y p ) n n 2 n 4 n + 1 n a / d i n p u t p i n p c b i n p u t p i n a / d c l o c k a / d o u t p u t p c b o u t p u t p i n p c b o u t p u t p i n p c b o u t p u t p i n p c b o u t p u t p i n v i n ( d i r . i n , a m p . i n ) c l k c l k c l k d 7 t o d 0 ( f o r 1 / 1 f r e q u e n c y d i v i s i o n ) c l k n c l k ( f o r 1 / 1 f r e q u e n c y d i v i s i o n ) d 7 t o d 0 d a t a o u t ( f o r 1 / 2 f r e q u e n c y d i v i s i o n ) c l k n c l k ( f o r 1 / 2 f r e q u e n c y d i v i s i o n ) t d h 1 . 8 n s ( t y p )
? 14 CXA1396D adjustment methods and notes on operation 1) vin offset (vr1) the volume to adjust the signal range (0v center assumed) with the a/d converter input range when a waveform is input through amp. in. 2) a/d full scale (vr2) the volume to adjust a/d converter vrb voltage. 3) linearity (vr3) the volume to adjust vrm (linearity) voltage. when dir. in input selected and it is supplied through the capacitor, vr3 can be used to adjust the input offset voltage. 4) d/a full scale (vr4) the volume to adjust d/a output full scale (?v). 5) j1 (input selection) a: shorts to adjust vrm voltage. b: shorts to supply dc voltage to vin. c: shorts to select amp.in input. d: shorts to select dir.in input. [jumper position at shipment] j1 j1 j1 a a a b b b c c c d d d 6) sw1 the switch for linv high/low. 7) sw2 the switch for minv high/low. 8) sw3 (decimation) the switch to select clock frequency decimation. switch position: decimation ratio 0: 1/1 1: 1/2 2: 1/4 3: 1/8 4: 1/16 9) sw4 (d/a inv) the switch for d/a converter output inversion. 0.1 f input through the buffer amplifier input through the buffer amplifier (when the linearity is adjusted) input through the capacitor (when the offset is adjusted using the dir in. at the evaluation board)
? 15 CXA1396D 10) rn10, rn11 and rn12 are not mounted at shipment. they are not required during evaluation. 11) waveform probe pins p5 and p8 through p28 are devised to facilitate gnd connection in order to reduce the distortion. as shown in the diagram below, the distance between the probe point and the gnd is 300 mil, and there is f 1.2mm through hole at each. the signal and gnd locations are suit for a tektronix gnd tip (part number 013-1185-00). fig. 3 12) d/a converter (ic13) input data (waveform probe pins p21 through p28) are the complementary signals of the decimated a/d converter outputs. those are inverted again in the d/a converter so that the direction of reproduced waveform can agree with the a/d input signal converter. 13) the part unmber of the digital output connector is kel 8830e-020-170s. a corresponding connector and cable assembly is junkosma kbo020mcg50bi. f 1 . 2 m m p r o b e p o i n t g n d 3 0 0 m i l
? 16 CXA1396D pcb circuit schematic i c 4 c l c 4 0 4 a j p 2 v ( d ) p 6 s w 1 l i n v a g n d f e r r i t e b e a d a g n d r 9 1 . 3 k v r 2 2 k c 8 0 . 1 a g n d 5 . 2 v ( a ) i c 1 - 2 t l 4 5 5 8 q 1 2 s a 9 7 0 7 6 8 5 4 c 9 0 . 1 a g n d + 5 v ( a ) a / d f u l l s c a l e r 6 2 4 0 i c 3 t l 4 3 1 c p r 8 5 1 0 v r 1 2 k 1 2 6 3 4 a g n d a g n d i c 1 - 1 t l 4 5 5 8 a g n d a g n d r 7 1 k 2 7 3 4 a g n d 6 d i r . i n a m p . i n a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d c 1 2 0 . 1 c 1 1 0 . 1 c 3 0 . 1 c 6 1 c 7 1 c 4 3 . 3 r 4 2 2 k r 5 / 1 1 k v i n o f f s e t r 2 2 4 0 r 1 5 1 r 1 2 5 1 r 1 1 4 3 r 1 0 5 1 0 + 5 v ( a ) 5 . 2 v ( a ) 5 . 2 v ( a ) p 2 d g n d j 1 b r n 1 5 1 r n 1 5 1 r n 1 5 1 r n 1 5 1 v c c 1 a o u t _ a o u t a i n _ a i n b o u t _ b o u t v e e v c c 2 c o u t c o u t _ c i n c i n _ v b b b i n b i n _ i c 8 : 1 0 h 1 1 6 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 v c c 1 q 2 q 3 c o u t _ d 3 d 2 s 2 v e e v c c 2 q 1 q 0 c l k d 0 d 1 c i n _ s 1 i c 5 : 1 0 h 1 3 6 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 v c c 2 e n a b l e _ x 3 x 2 x 1 x 0 a v e e v c c 1 z x 7 x 6 x 5 x 4 c b i c 7 : 1 0 h 1 6 4 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 c 5 0 . 1 c 2 0 . 1 c 1 0 0 . 1 c 1 4 0 . 1 c 1 3 0 . 1 r n 1 d g n d d g n d r 3 5 1 d g n d 5 . 2 v ( d ) d g n d d g n d d g n d 5 . 2 v ( d ) d g n d d g n d d g n d c 2 2 0 . 1 d g n d 5 . 2 v ( d ) d g n d c 2 1 0 . 1 c 3 7 0 . 1 d g n d c 2 3 0 . 1 r 1 4 5 1 2 v ( d ) d g n d 2 v ( d ) d g n d r n 2 5 1 r n 2 5 1 r n 2 5 1 r n 2 5 1 r n 2 d g n d d g n d 2 v ( d ) d g n d c 3 1 0 . 1 r 1 8 5 1 s w 3 d e c i m a t i o n c 3 0 0 . 1 c 2 9 0 . 1 d g n d c 1 0 . 1 5 . 2 v ( d ) d g n d d 3 d 2 d 1 l h p 1 1 p 1 2 d 1 c l k d g n d p 1 3 d 2 r 1 5 3 3 0 2 8 3 1 3 2 n c v r b n c a v e e a v e e n c n c a g n d v i n a g n d v r m a g n d v i n a g n d n c n c a v e e a v e e n c v r t n c i c 6 : c x a 1 3 9 6 d 4 0 3 9 3 8 3 7 3 6 3 3 4 1 4 2 c l k c l k n n c m i n v d v e e d g n d 1 d g n d 2 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d g n d 2 d g n d 1 d v e e l i n v n c a v e e p 1 0 s w 2 m i n v c 2 4 0 . 1 c 2 6 1 c 2 5 0 . 1 f e r r i t e b e a d d 3 d 0 c 2 2 0 . 1 d g n d 2 v ( d ) r 1 7 5 1 r 1 6 5 1 5 . 2 v ( d ) 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 3 4 5 6 7 8 1 p 1 7 p 1 6 p 1 5 p 1 4 d 6 d 7 d 4 d 5 p 9 c l k p 8 c l k n c 1 9 0 . 1 c 2 0 1 0 a g n d c 1 8 0 . 1 5 . 2 v ( a ) 2 2 2 3 2 4 2 5 2 6 2 7 a g n d 2 9 3 0 c 1 7 0 . 1 a g n d p 5 p 4 a g n d a g n d v i n p 3 a v e e 5 . 2 v ( a ) a g n d c 1 5 1 c 1 6 0 . 1 a d c r 1 3 1 k a g n d p 1 v r b v r m v r 3 1 k 3 5 3 4 5 . 2 v ( d ) 5 . 2 v ( a ) c 2 5 0 . 1 c 2 7 0 . 1 d g n d d g n d p 1 7 d v e e l i n e a r i t y # 1 # 2 # 3 # 4 # 5 # 6 # 7 # 8 # 9 # 1 0 # 1 1 # 1 2 # 1 3 # 1 4
? 17 CXA1396D m s b d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 l s b n c n c c l k n c l k a g n d 2 v r e f a v e e n c n c n c n c n c o u t n c a g n d 1 d g n d i n v d v e e r n 1 1 5 1 d g n d d g n d d 0 d g n d d 1 d g n d d 2 d g n d d 3 d g n d d 4 d g n d d 5 d g n d d 6 d g n d d 7 d g n d c l k d g n d d i g i t a l o u t c o n n e c t o r k e l : 8 8 3 0 e - 0 2 0 - 1 7 0 s ( t o p v i e w ) r n 1 0 7 5 r n 1 0 7 5 r n 1 0 7 5 r n 1 0 7 5 r n 1 0 r n 1 1 5 1 r n 1 1 5 1 r n 1 1 5 1 r n 1 1 r n 1 2 5 1 r n 1 2 r n 1 2 5 1 r n 1 2 5 1 r n 1 2 5 1 c 5 2 0 . 1 d g n d 2 v ( d ) c 5 3 0 . 1 2 v ( d ) d g n d 2 v ( d ) d g n d c 5 1 0 . 1 2 0 1 6 1 2 8 4 6 1 0 1 3 1 4 1 8 p 2 9 c 5 4 3 3 d g n d 2 v ( d ) 2 v ( d ) p 3 0 d g n d d g n d d g n d p 3 1 c 5 5 3 3 d g n d 5 . 2 v ( d ) 5 . 2 v ( d ) p 3 2 c 5 6 3 3 a g n d 5 . 2 v ( a ) 5 . 2 v ( a ) p 3 3 a g n d a g n d p 3 4 c 5 7 3 3 a g n d + 5 v ( a ) + 5 v ( a ) a g n d i c 1 3 : c x 2 0 2 0 2 a - 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 1 r n 9 7 5 r n 9 7 5 r n 9 7 5 r n 9 7 5 r n 8 7 5 r n 8 7 5 r n 8 7 5 r n 8 7 5 r n 8 c 4 4 0 . 1 d g n d 2 v ( d ) 2 v ( d ) c 4 6 0 . 1 c 4 7 0 . 1 5 . 2 v ( d ) d g n d d g n d d g n d d / a o u t s w 4 d / a i n v d 4 d 6 d 5 r 2 3 3 . 2 k 5 . 2 v ( d ) p 2 3 p 2 4 p 2 5 p 2 6 p 2 7 p 2 8 c 4 5 0 . 1 d g n d 2 v ( d ) 5 . 2 v ( a ) a g n d r 2 2 2 4 0 c 5 0 3 3 c 4 9 0 . 1 d / a f u l l s c a l e c 4 8 0 . 1 r 2 1 1 k v r 4 2 k i c 1 4 t l 4 3 1 c p d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r n 7 5 1 r n 7 5 1 r n 7 5 1 r n 7 5 1 c 4 3 0 . 1 d g n d r n 7 p 1 9 p 2 0 c l k n c l k a g n d d g n d a g n d r n 9 d g n d l h v c c 1 q 0 q 1 q 2 d 0 d 1 d 2 v e e v c c 2 q 5 q 4 q 3 d 5 d 4 d 3 c l k 2 3 4 8 9 1 1 1 2 1 3 1 4 1 5 1 6 1 v c c 1 q 0 q 1 q 2 d 0 d 1 d 2 v e e v c c 2 q 5 q 4 q 3 d 5 d 4 d 3 c l k i c 9 : 1 0 h 1 7 6 2 3 4 8 9 1 1 1 2 1 4 1 5 1 6 1 d g n d d g n d d g n d c 2 4 0 . 1 d g n d 5 . 2 v ( d ) c 2 6 0 . 1 d g n d 5 . 2 v ( d ) v c c 2 d o u t _ c o u t _ d i n c o m i n c o u t c i n d o u t v c c 1 a o u t _ b o u t _ a i n a o u t b o u t b i n v e e i c 1 2 : 1 0 h 1 0 1 2 3 4 5 7 8 1 0 1 2 1 3 1 4 1 5 1 6 1 v c c 1 a o u t _ b o u t _ a i n a o u t b o u t b i n v e e v c c 2 d o u t _ c o u t _ d i n c o m i n c o u t c i n d o u t i c 1 1 : 1 0 h 1 0 1 2 3 4 1 2 1 4 1 5 1 6 1 c 3 9 0 . 1 d g n d 5 . 2 v ( d ) d g n d d g n d d g n d c 4 1 0 . 1 d g n d 5 . 2 v ( d ) d g n d d g n d r n 4 7 5 r n 4 7 5 r n 4 7 5 d g n d c 3 6 0 . 1 2 v ( d ) r n 4 7 5 r n 4 r n 6 7 5 r n 6 7 5 r n 6 7 5 d g n d c 4 2 0 . 1 2 v ( d ) r n 6 7 5 r n 6 r n 5 7 5 r n 5 7 5 r n 5 7 5 d g n d c 4 0 0 . 1 2 v ( d ) r n 5 r n 3 7 5 r n 3 7 5 r n 3 7 5 d g n d c 3 5 0 . 1 2 v ( d ) r n 3 7 5 r n 3 v c c 1 a o u t _ a o u t a i n _ a i n b o u t _ b o u t v e e v c c 2 c o u t c o u t _ c i n c i n _ v b b b i n b i n _ i c 8 : 1 0 h 1 1 6 2 3 4 5 8 9 1 0 1 1 1 2 1 3 1 6 1 d g n d 5 . 2 v ( d ) c 3 4 0 . 1 d g n d 2 v ( d ) c 3 8 0 . 1 d g n d d g n d r 2 0 5 1 d g n d c 3 7 0 . 1 1 7 1 9 c l k n 1 4 1 5 p 1 8 r 1 9 5 1 2 v ( d ) c l k 9 1 2 7 3 5 1 5 1 1 1 1 6 9 1 1 1 0 9 1 3 5 6 7 8 i c 1 0 : 1 0 h 1 7 6 5 6 7 1 0 p 2 1 p 2 2 6 7 5 6 7 1 0 r n 5 7 5 # 1 # 2 # 3 # 4 # 5 # 6 # 7 # 8 # 9 # 1 0 # 1 1 # 1 2 # 1 3 # 1 4 1 3
? 18 CXA1396D characteristic graph f i g . 5 . g a i n v s . i n p u t f r e q u e n c y ( c l k = 1 2 5 m h z ) g a i n [ d b ] 2 0 2 4 6 8 1 0 1 0 1 0 0 i n p u t f r e q u e n c y [ m h z ] f i g . 6 . s n r v s . i n p u t f r e q u e n c y ( c l k = 1 2 5 m h z ) s n r [ d b ] 5 0 4 5 4 0 3 5 3 0 2 5 2 0 1 0 1 0 0 i n p u t f r e q u e n c y [ m h z ] d i r . i n a m p . i n 1 f i g . 7 . 2 n d , 3 r d h a r m o n i c d i s t o r t i o n v s . i n p u t f r e q u e n c y ( c l k = 1 2 5 m h z ) 2 n d , 3 r d h a r m o n i c d i s t o r t i o n [ d b ] 2 0 3 0 4 0 5 0 6 0 7 0 8 0 1 0 1 0 0 i n p u t f r e q u e n c y [ m h z ] 2 n d d i r . i n 2 n d a m p . i n 3 r d d i r . i n 3 r d a m p . i n 1 measurement data figs. 5, 6 and 7 show the characteristic graphs. dir. in is the characteristic where the signal is directry input to the adc and amp. in is the characteristic where the signal is input to adc through the amplifier.
? 19 CXA1396D parts layout
? 20 CXA1396D 1st layer component plane (top view) 4th layer solder plane (top view) printed pattern
? 21 CXA1396D 2nd layer gnd plane (top view) 3rd layer power supply plane (top view)
? 22 CXA1396D package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e w e i g h t g o l d p l a t i n g 4 2 a l l o y 4 2 p i n d i p ( c e r a m i c ) 6 0 0 m i l 5 3 . 4 0 . 5 1 3 . 2 0 . 2 2 . 5 4 2 1 2 2 4 2 1 0 . 4 6 0 . 1 1 . 0 0 . 1 3 . 3 m i n 1 . 0 m i n 6 . 6 m i n 6 . 9 1 m i n 1 5 . 2 4 0 . 2 5 0 . 2 5 + 0 . 0 5 0 . 0 2 0 t o 1 5 6 . 7 g d i p - 4 2 c - 0 1 * d i p 0 4 2 - c - 0 6 0 0 - a c e r a m i c

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